Due to advancements in processing technology, complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware descriptive language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the design is often structured in an object oriented manner. The designer describes a module in terms of the behavior of a system describing signals that are generated and propagated through combinatorial modules from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher level modules.
An HDL design can be synthesized to create a logical network list (netlist), which can be implemented within a particular programmable logic device. Alternatively, the HDL design can be simulated to determine whether the design will function as required using a logic simulator. A logic simulator is a software tool capable for performing functional and timing simulation of an HDL circuit design.
Before an HDL design can be synthesized into a netlest or simulated, the design must go through the preparatory processes of analysis and elaboration. In the analysis process, the HDL design is examined to determine if it contains syntax or semantic errors. If no errors are discovered, the analyzer creates an intermediate representation of each design module and stores the intermediate representations in a library.
In the elaboration process, the design is reduced to a collection of signals and processes. Each logic component is constructed and connections between logic components are established. This is generally done by parsing the design. For each instance of a design module encountered during parsing, a data structure is created for the instance and placed into a parse tree. The data structure implementing an instance contains the processes of the module, variables used by those processes, and variables representing input and output signals from the module instance. Memory is allocated to store the processes and signal variables and initial values that are assigned to the signal variables. The location or offset of the allocated memory is stored within the data structures. Following elaboration, executable simulation code is compiled or synthesized from the process data files stored in a process library using the memory addresses and initial values allocated and assigned to the module instances.
Due to the increasing complexity and size of HDL designs, the elaboration required for synthesis or simulation requires large amounts of memory. The present invention may address one or more issues introduced by current elaboration approaches.